ARM Accredited engineer (EN0-001) Free Practice Test
Question 1
Which of the following register values would cause an unaligned access when the instruction LDRH r0, [r1] is executed?
Correct Answer: A
Question 2
If a 16-bit Thumb instruction causes a Data Abort, which instruction would return from the handler to the instruction after the one that caused the data abort?
Correct Answer: D
Question 3
When using an Operating System, which instruction is used by user code to request a service from the kernel?
Correct Answer: B
Question 4
Capturing processor execution trace is characterized as being:
Correct Answer: A
Question 5
The following pseudocode sequence shows a flag being set to indicate that new data is ready to be read by another thread:
data = 123;
ready = true;
Assuming that the reader threads may execute on any other core of a multicore system, which of the following is the most efficient memory barrier to place between the two writes to prevent them being observed in the opposite order?
data = 123;
ready = true;
Assuming that the reader threads may execute on any other core of a multicore system, which of the following is the most efficient memory barrier to place between the two writes to prevent them being observed in the opposite order?
Correct Answer: C
Question 6
According to the EABI. what would the C size of () operator return when given the following structure?


Correct Answer: D
Question 7
When timing a critical function for an algorithm, using platform time functions such as get time of day (), the result is unpredictable; there is significant variance in the measured time between different runs of the benchmark. Which of the following strategies would improve the accuracy of the measurement?
Correct Answer: D
Question 8
In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:
-CPU 0 and 1 are sleeping in low-power state following a WFI instruction. . CPU 2 is executing program code. -CPU 3 is sleeping in low-power state following a WFE instruction.
CPU 2 executes a SEV instruction. What is the effect on the system?
-CPU 0 and 1 are sleeping in low-power state following a WFI instruction. . CPU 2 is executing program code. -CPU 3 is sleeping in low-power state following a WFE instruction.
CPU 2 executes a SEV instruction. What is the effect on the system?
Correct Answer: B
Question 9
Which TWO of the following options can the ARM Compiler (armcc) directive__packed be used for? (Choose two)
Correct Answer: A,C
Question 10
Which of the following statements regarding Strongly-ordered memory is architecturally FALSE?
Correct Answer: A
Question 11
Printf statements could be used to achieve which of the following debug tasks?
Correct Answer: C